The present invention relates to a method for fabricating a floating gate memory.
One of the key process issues for realizing high performance analog and digital circuits is the ability to fabricate precision, high value, polysilicon to polysilicon capacitors at the same time as low resistance polysilicon gates and interconnects.
A common technique for producing polysilicon to polysilicon capacitors is to lightly dope the first level of polysilicon (bottom plate) to 100 ohms per square, so a very uniform dielectric can be grown on polysilicon at the same time the gate oxide is regrown. Second level polysilicon is then used as the top plate.
The main limitation with this technique is that the capacitor's dielectric thickness, and hence maximum value, is controlled by the regrown gate oxide thickness. For a 700 A gate oxide process this increases the dielectric to about 1100 A (oxide grows faster on doped polysilicon, resulting in a capacitance of 0.2 pF/mil.sup.2.
This problem is particularly acute in floating gate memories, such as EPROMs, EEPROMSs, and other floating gate technologies. Such floating gate technologies are widely used to achieve a nonvolatile memory by storing charge in the floating gate by tunnel or avalanche injection through a thin dielectric adjacent to the gate, usually a dielectric between the gate and the substrate.
In such memories, normally a reverse process is used. That is, the first polysilicon level is used for the floating gates which are totally encapsulated and isolated portions of polysilicon. The control gates for each cell, and any other necessary transistors, are formed in the second polysilicon level.
As floating memories are scaled down, the problem is to lower the operating voltage while retaining essentially the same voltage swing on the floating gate. That is, if the write voltage which can be applied to the control gate is scaled down from 20 volts to 15 volts, it is highly desirable to be able to still apply the same voltage swing to the floating gate with a 15 volt control signal as was previously possible with a 20 volt control signal. To accomplish this, very close coupling between the floating gate and the control gate is required. This in turn requires very high specific capacitance between the floating gate and the control gate.
A complicating factor in achieving this necessary high specific capacitance is that a very good quality insulator is needed. Not only is integrity essential under the high dielectric stress imposed by the high voltages necessarily used for writing in a floating gate memory, but also leakage between the floating gate and the control gate imposes another very important parameter. That is, since information is stored by charges trapped in the floating gate, one of the critical limitations on device performance is imposed by the leakiness of the dielectric between the floating gate and the control gate, since this provides one of the critical leakage paths.
Thus it is an object of the present invention to provide a floating gate memory cell having a very high specific capacitance between the floating gate and the control gate.
It is a further object of the present invention to provide a floating gate memory cell in which the specific capacitance between the floating gate and the control gate is very high, and the dielectric integrity between the floating gate and the control gate is also very high.
It is further object of the present invention to provide a method for fabricating a floating gate memory cell in which the specific capacitance between the floating gate and the control is very high in which the leakage resistance between the floating gate and the control gate is also extremely high.
A further difficulty in the prior art of floating memories is that many floating gate memory processes have strayed far afield into the realm of exotic processing techniques. While the requirement of injecting charge through an insulator into the floating gate necessarily requires some unusual processing techniques, to provide a good quality dielectric and to withstand the high write voltages required, exotic fabrication processes can impose a heavy burden of reliability and cost.
Thus it is an object of the present invention to provide a method for fabricating capacitors having high specific capacitance for large and high dielectric strength.
It is further object of the present invention to provide a method for fabricating capacitors having high specific capacitance in a standard MOS process. Forming a precision capacitor over a first polysilicon level is particularly difficult, since the surface of the first polysilicon level will never be as smooth as that of a monocrystalline polished semiconductor surface, that is, the surface of even good polysilicon will normally have a certain amount of unevenness. This unevenness can significantly affect the thickness of an oxide which is formed over the polysilicon. It not only leads to uncertainty in the average specific capacitance, but also can cause formation of areas where an oxide grown over polysilicon is locally thin.
Thus it is a further object of the present invention to provide a method for reliable fabrication of uniform dielectrics over a polysilicon level. The roughness of the polysilicon surface means that pinholing through a dielectric grown over first polysilicon can occur. This problem becomes particularly serious if the dielectric is a thin one, as is required for high specific capacitance. This is a major concern in floating gate memories, since the large total area devoted to capacitors means that even a small density of capacitor pinholes can cause drastic yield degradation.
Thus it is a further object of the present invention to provide a thin polysilicon-to-polysilicon dielectric having a very low density of pinholes.
In double polysilicon processes, a regrown gate oxide is normally used to form transistors having second polysilicon gates. That is, after the first polysilicon level has been completely formed, the areas where transistors in second polysilicon are to be formed are cleared down to silicon, and the gate oxides for second polysilicon transistors are grown from scratch. However, the oxidizing conditions which permit growth of the second gate oxide also promote growth of oxide over the first polysilicon level. Moreover, oxide normally grows faster on doped polysilicon than to crystalline silicon under the same conditions, so that a thicker oxide will be formed over the first polysilicon level. Where the oxide has already been formed over the first polysilicon level before growth of the second gate oxide, as is typical, the oxide thickness over the first polysilicon will be increased by the oxidizing conditions.
The second gate oxide will of course normally be grown to a precisely controlled thickness, but the simultaneous thickness increase of the oxide over the first polysilicon may be poorly controlled. The chief reason for this is because of doping uncertainty. The oxidizing rate is a function of the polysilicon doping level, and the doping level itself cannot be precisely controlled in highly conductive POCl.sub.3 -doped polysilicon. Even if the polysilicon doping is performed by ion implantation, the average doping level in polysilicon will still be sensitive to the thickness of the polysilicon level deposited, which is also normally not a parameter which can be precisely controlled.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without any uncontrolled change in the thickness of an existing oxide over a first polysilicon level.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without simultaneously growing a thick oxide over first polysilicon.
It is further object of the present invention to provide a method for growing a second gate oxide without increasing the thickness of a dielectric over a first polysilicon level.
In the present invention a composite oxide/nitride or oxide/nitride/oxide dielectric is used over the first polysilicon level instead of the thermal oxide taught by the prior art. This means that very thin dielectrics can be used over first polysilicon which have very high dielectric integrity (low level of pinholes) and very high dielectric strength (breakdown voltage). Moreover, the dielectrics formed by the present invention are virtually unaffected by the normal second gate oxide growth cycle, so that the problem of uncontrolled thickness increase vanishes.
The problems described above are exacerbated in high voltage circuits, and particularly in floating gate memory circuits. Since the second oxide thickness must be extremely high in these circuits anyway to prevent gate/drain breakdown and excessive injection of hot carriers into the second gate oxide, the problem of thickening of the oxide over the first polysilicon during the growth of the second polysilicon is exacerbated. That is, a typical thickness for the second gate oxide in a high voltage (21 volt) EEPROM process would be 600 angstroms, and while 600 angstroms of oxide are grown on silicon typically 1000 angstroms will be grown on doped polysilicon, or the thickness of an existing oxide layer on poly would be increased.
The present invention fabricates improved floating gate memory cells using high voltage poly to polysilicon capacitors with a much higher capacitance/unit area, e.g. 0.8 pG/mil.sup.2. The technique utilizes a composite oxide/nitride/oxide dielectric whose thickness is controlled independently of the regrown gate oxide, without the requirement of an extra mask. The composite dielectric has very good integrity; typical breakdown for a 350 A composite layer is 24-30 V. Leakage measurements indicate characterisitics similar to polysilicon capacitors with an 800 A thermally grown oxide. In some of the test experiments the oxide and nitride layers were formed by LPCVD. These have exhibited high uniformity, better than 0.005% mil or 3% across a 3" slice. A further advantage of using an LPCVD dielectric is that first polysilicon can be doped to about 15 ohms per square since it is no longer necessary to thermally grow a uniform oxide. This gives the designer the flexibility of using both heavily doped 1st polysilicon and silicided 2nd polysilicon for interconnect.
It is a further object of the present invention to provide a method for fabricating high voltage MOS integrated circuits, in which the thickness of the dielectric between the first and second polysilicon levels can be selected to be equal to or less than the thickness of the second gate oxide.
A method for making a floating gate memory, comprising the steps of:
providing a semiconductor substrate; PA1 forming a first gate insulator layer on said substrate; PA1 forming a first insulated conductor layer over said substrate, said conductor layer being polycrystalline and comprising silicon; PA1 forming a layer of silicon dioxide over said first conductive layer; PA1 forming a layer of silicon nitride over said first conductive layer; PA1 patterning said first insulated conductor layer, to define a plurality of desired floating gate; PA1 providing an oxidizing atmosphere to form gate insulators in selected locations; PA1 forming a second conductive layer in predetermined locations, said second conductive layer comprising control gate portions over said floating gates in said first conductive layer; and PA1 implanting a plurality of source and drain regions on opposite sides of the respective ones of said floating gates; PA1 whereby a floating gate memory cell having very high specific capacitance between said respective floating gates and said respective control gates in formed.